• What is VLSI and its role?
• End to End Flow: Front-end and Back-end

• Gate Basics
• PMOS, NMOS and CMOS
• Logic Modeling with Standard cells
• Processing: Bulk CMOS, FD-SOI, FinFet
• ASIC: Custom and Semi-Custom
• ASIC and FPGA

1. Introduction
    1. What Is System
    2. What Is Digital System
    3. Why Digital System Is Needed
2. Number System
    1. What Is Number Systems
    2. Binary Number System
    3. Signed And Unsigned Numbers
    4. Complementary Numbers
    5. Range Of Numbers
    6. Octal And Hexadecimal Numbers
3. Binary Codes
    1. Self-Complementary Codes
    2. Excess 3 Code
    3. Gray Code
    4. Code Conversions
4. Boolean Algebra And Logic Gates
    1. 3 D's Properties
    2. Importance Of Ex-or Gate
    3. Sop And Pos Realisations
5. Combinational Circuits
    1. Introduction
    2. Design Procedure
    3. Decoders
    4. Encoders
    5. Mux And Demux
    6. Universal Function Generator And Simplification
    7. Barrel Shifter/Combinational Shifter
6. Adders
    1. Half Adder
    2. Full Adder
    3. Ripple Carry Adder
    4. Carry Save Adder
    5. Carry Select Adder
    6. Carry Look Ahead Adder
    7. Bcd Adder
    8. 4 Bit Adder/Subtractor
7. 2 Bit Magnitude Comparator
8. Binary Multiplier
    1. Regular Multiplication And Challenges
    2. Csa Based Multiplication
    3. Multiplication As Algorithm
    4. Radix 2 Booth's Algorithm
    5. Radix 4 Booth's Algorithm
9. Sequential Circuits
    1. Introduction And Definition
    2. Latches
        1. S R Latch
        2. D Latch
        3. S'r' Latch
        4. Clocked Sr Latch
    3. Flip Flop
        1. D Flip Flop
        2. T Flip Flop
    4. Propagation Delay Of Flip Flops
    5. Set Up Time, Hold Time Of Flip Flops
    6. Registers
    7. Shift Registers
        1. Siso Register
        2. Piso Register
        3. Sipo Register
        4. Pipo Register
    8. Counters
        1. Synchronous Counters
        2. Asynchronous Counters
        3.  Up Counter/Down Counter
        4. Modulo Counter
        5. Applications Of Counters
        6.  Counting No. Of. Pulses
        7. Frequency Division
10. Finite State Machines
    1. Introduction
    2. Moore FSM
    3. Mealy FSM
    4. Applications Of FSM's
    5. Sequence Detector Using FSM
11. Memory
    1. Introduction
    2. Classification Of Memory
    3. Rom
        1. Prom
        2. Eprom
        3. Eeprom
        4. Flash Memory
    4. Ram
        1. Sram
        2. Dram
        3. Sdr
        4. Ddr
            1. Ddr1
            2. Ddr2
            3. Ddr3
            
180+ Assignments 

6 Exams

1. Digital Fundamental
2. Combinational Level -1
3. Combinational Level -2
4. Sequential Level -1
5. Sequential Level -2
6. Digital Design Grand Test

All Digital System Design Module Training as listed above Click here to go

1. Hardware Description Language (HDL)
2. Introduction & Importance of HDL - HDL vs. High Level Languages 
3. Logic Design using Verilog / Design Methodologies Verilog – Introduction
4. Basic Language elements - Design constraints
   1. Data types- Simple and complex
   2. Wires and registers
   3. Hardware orientation
5. Parts of Code in Verilog
6. Modules & Ports 
7. Body and Concurrency
8. Modeling styles in Verilog
   1. Data flow
      1. continuous assign
      2. Event Triggering introduction
   2. Gate-level
      1. primitive gates and instantiation
      2. Event Triggering 
   3. Structural
      1. Module vs Component
      2. Component instantiation and types
      3. Event Triggering
   4. Behavioral
      1. Introduction to procedural programming
      2. Initial and Always
      3. Always use cases and deeper study with event triggering
      4. Blocking and non-blocking
      5. Tasks & Functions
      6. Forks
9. Advanced Verilog Topics
   1. Compiler Directives
   2. Test bench and clock generation
10. Verilog Theoretical  Exams
    1. Level 1
    2. Level 2
11. Verilog Labs
    1. Level 1
    2. Level 2
    3. Level 3
12. Basic Interview Questions Discussion
13. Advanced Interview Questions Discussions
14. Mock Interview -2

• Designing Strategies
• Emphasis on Simulation & Synthesis Issues
• RTL Design Strategies (VHDL & Verilog)
• Static Timing Analysis (STA) 
• Linux Essentials and TCL
• Lint and CDC

• Literature Survey
• Architecture 
• Micro Architecture
• Module Development
• Simulation and STA
• Synthesis and Validation
• Requirement Matching for Design parameters and Fine tuning
• Project presentation

• Introduction to Programmable Logic Devices
• Study of PLD’s, CPLD’s
• Introduction to FPGA - Design Flow & Overview
• FPGA Implementation (Board Level Explanation) 
• FPGA Implementation of Mini Projects 

• Presentation preparation
• Results Explanation

• Verification - Introduction & Importance 
• Verification Methodologies
• Verification Process 
• Reusable TB 

1. Introduction To System Verilog
1. Data Types
2. Operators
2. Arrays
1. Fixed Size Array
2. Dynamic Array
3. Associative Arrays
4. Queues
5. Array Methods
3. Procedural Statements & Control Flow 
1. Blocking & Non-Blocking If Priority If
2. Loops
1. For & Foreach
2. While & Do-while 
3. Repeat
4. Forever 
5. Break And Continue
3. Named Blocks
4. Statement Labels
5. Disable Blocks
6. Disable Statements
7. Event Control
4. Processes
1. Fork
2. Forkjoin, Fork Join None 
5. Tasks
6. Functions
7. Oops Fundamentals 
8. Class, Constructor, This Keyword
9. Static Class Properties & Methods
10. Class Assignment, Shallow Copy, Deep Copy
11. Inheritance, Polymorphism, Data Hiding Encapsulation
12. Sv Tb Architecture
1. Generator
2. Driver Monitor
3. Agent
4. Scoreboard EnvironmentTest And Tb_Top
13. Sv Tb Architeure Code Templates
14. Randomization & Constraints 
1. Randomization Concept Methods Constraint And Constraint Methods 
2. Inside, Dist, Inline, If Else Implication Constraints 
3. Iterative, Functional, Soft, Unique, Solve Before Constraints
15. Inter-Process Communication
1. Mailbox
2. Semaphore
3. Event
4. Multiple Process Threading
16. Interface, Modport, Clocking Blocks
17. Assertions
1. Concept, Need Of Assertions, Assertion Building Blocks
2. Implication And Replication Operator
3. Ended Iff, Disable Iff, Sva Built-In Methods 
18. Functional Coverage 
1. Concept, Types Of Coverage
2. Coverage Model Cover Group Definition
3. Transitional Coverage, Cross Coverage
19. Miscellaneous Topics
20. Sv Example Coding 
21. Basic Interview Questions Discussion 
22. Advanced Interview Questions Discussion
23. Real-Time Project Explanation
24. Feature Extraction / Testcase Plan

• What, Why and How of UVM
• UVM TB Architecture
• Phases and TLM
• Arbitration and Sequencer
• UVM Macros